The invention relates to an integrated circuit chip with built-in self-test for logic fault detection which comprises at least one combinational logic circuit.
Cordt W. Starke, "Design for testability and diagnosis in a VLSI CMOS System/370 processor", IBM Journal of Research and Development, Volume 34, Number 2/3, March/May 1990, pages 355 to 362, describes a design of combinational logic circuits which incorporates on-chip test pattern generation and on-chip test response evaluation for logic fault detection. In this paper, the combinational logic circuits are coupled together in a typical level-sensitive scan design (LSSD) by shift register latches (SRL's) which are configured to form test scan paths. The test patterns are generated by a linear feedback shift register (LFSR) which is configured as a pseudo-random pattern generator and which is implemented on the chip. To apply a test pattern, the shift register latches are loaded via the test scan paths. Then, the system clocks are pulsed once in order to execute one operational cycle of the system. After the system clocks have been applied, the test response is shifted out of the shift register latches via the test scan paths for further evaluation. However, the paper does not describe any weighting of the pseudo-random test patterns.
Robert W. Bassett et. al., "Low-cost testing of high-density logic components", "IEEE Design & Test of Computers", April 1990, pages 15 to 27, describes a weighted random pattern tester (WRPT) for combinational logic circuits with shift register latches (SRL's) and level-sensitive scan design (LSSD). The test patterns are generated by a linear feedback shift register (LFSR) and are then passed to a weight logic which is connected to a weight storage table. This table contains test weights for any shift register latch of the combinational logic circuit. The stored test weights are combined with the test patterns and are then applied to the shift register latches. Again, the system clocks are pulsed once and the test response is shifted out for evaluation and fault detection. Especially due to the weight storage table, the tester described in this paper requires substantially more hardware than an unweighted tester and therefore the tester cannot be placed on the chip.
It is an object of the invention to provide an integrated circuit chip with built-in self-test and weighted pseudo-random test patterns for logic fault detection.